Allan.J.Wilson: #Digital Electronics

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Sunday, 22 November 2020

Digital Logic Circuits MCQs

In which of the following gates, the output is 1, if and only if at least one input is 1?

A.	NOR
B.	AND
C.	OR
D.	NAND
	Answer
	Option: C Explanation : In OR gate we need atleast one bit to be equal to 1 to generate the output as 1 because OR means any of the condition out of two is equal to 1 which means if atleast one input is 1 then it shows output as 1 . Number of 1's in input may be more than one but the output will always be 1 in OR gate. So the answer is 'C'. .

2: The time required for a gate or inverter to change its state is called

A.	Rise time
B.	Decay time
C.	Propagation time
D.	Charging time
	Answer
	Option: C Explanation : .

3: The time required for a pulse to change from 10 to 90 percent of its maximum value is called

A.	Rise time
B.	Decay time
C.	Propagation time
D.	Operating speed
	Answer
	Option: A Explanation : .

4: The maximum frequency at which digital data can be applied to gate is caled

A.	Operating speed
B.	Propagation speed
C.	Binary level transaction period
D.	Charging time
	Answer
	Option: A Explanation : .

What is the minimum number of two-input NAND gates used to perform the function of two input OR gate ?

A.	one
B.	two
C.	three
D.	four
	Answer
	Option: C Explanation : Y=A+B. This is the equation of OR gate. We require 3 NAND gates to create OR gate. We can also write After 1^st NAND operation Y = (A AND B)' Y= A' + B' (Demorgan's Law) After 2^nd NAND operation Y= ( A' + B')' Y= A . B (Demorgan's Law) After 3^rd NAND operation Y= ( A . B )' Y= A' + B ' (Demorgan's Law) So we need 3 NAND gates.

6: Odd parity of word can beconveniently tested by

A.	OR gate
B.	AND gate
C.	NOR gate
D.	XOR gate
	Answer
	Option: D Explanation : .

Identify the logic function performed by the circuit shown in the given figure

A.	Exclusive OR
B.	Exclusive NOR
C.	NAND
D.	NOR
	Answer
	Option: B Explanation : .

8: Which one of the following will give the sum of full adders as output ?

A.	Three point majority circuit
B.	Three bit parity checker
C.	Three bit comparator
D.	Three bit counter
	Answer
	Option: D Explanation : .

The number of full and half-adders required to add 16-bit numbers is

A.	8 half-adders, 8 full-adders
B.	1 half-adder, 15 full-adders
C.	16 half-adders, 0 full-adders
D.	4 half-adders, 12 full-adders
	Answer
	Option: B Explanation : The one half-adder can add the least significant bit of the two numbers. Full adders are required to add the remaining 15 bits as they all involve adding carries. .

10: The time required for a pulse to decrease from 90 to 10 per cent of its maximum value is called

A.	Rise time
B.	Decay time
C.	Binary level transition period
D.	Propagation delay
	Answer
	Option: B Explanation : .

11: Which of the following gates would output 1 when one input is 1 and other input is 0 ?

A.	OR gate
B.	AND gate
C.	NAND gate
D.	both (a) and (c)
	Answer
	Option: D Explanation : .

12: Which of the following statements is wrong ?

A.	Propagation delay is the time required for a gate to change its state
B.	Noise immunity is the amount of noise which can be applied to the input of a gate without causing the gate to change state
C.	Fan-in of a gate is always equal to fan-out of the same gate
D.	Operating speed is the maximum frequency at which digital data can be applied to a gate
	Answer
	Option: C Explanation : .

13:

Which of the following expressions is not equivalent to X ' ?

A.	X NAND X
B.	X NOR X
C.	X NAND 1
D.	X NOR 1
	Answer
	Option: D Explanation : Answer is C as if X= 0 then X NAND 1 = 1 = X ' if X=1 then X NAND 1= 0= X' In Option (d) if X= 0 then X NOR 0 = 1 = X' if X=1 then X NOR 1= 0 <> X' .

14: Which of the following gates are added to the inputs of the OR gate to convert it to the NAND gate ?

A.	NOT
B.	AND
C.	OR
D.	XOR
	Answer
	Option: A Explanation : .

15: The EXCLUSIVE NOR gate is equivalent to which gate followed by an inverter ?

A.	OR
B.	AND
C.	NAND
D.	XOR
	Answer
	Option: D Explanation : .

16:

A one-to-four line demultiplexer is to be implemented using a memory. How many bits must each word have ?

A.	1 bit
B.	2 bits
C.	4 bits
D.	8 bits
	Answer
	Option: A Explanation : 2 select line A and B will work as address lines, so we have 4 addresses (or words) Each word will have 4 bits so memory required is 4 x 4 = 16 bits .

17: What logic function is produced by adding an inverter to the output of an AND gate ?

A.	NAND
B.	NOR
C.	XOR
D.	OR
	Answer
	Option: A Explanation : .

18: Which of the following gates is known as coincidence detector ?

A.	AND gate
B.	OR gate
C.	NOT gate
D.	NAND gate
	Answer
	Option: A Explanation : .

19: Which table shows the logical state of a digital circuit output for every possible combination of logical states in the inputs ?

A.	Function table
B.	Truth table
C.	Routing table
D.	ASCII table
	Answer
	Option: B Explanation : .

20:

A positive AND gate is also a negative

A.	NAND gate
B.	NOR gate
C.	AND gate
D.	OR gate
	Answer
	Option: D Explanation : Truth Table For AND 0 0 => 0 0 1 => 0 1 0 => 0 1 1 => 1 Now invert all values (as if you place inverters on the two inputs and the one output): 1 1 => 1 1 0 => 1 0 1 => 1 0 0 => 0 .

21:

A demultiplexer is used to

A.	Route the data from single input to one of many outputs
B.	Perform serial to parallel conversion
C.	Both (a) & (b)
D.	Select data from several inputs and route it to single output
	Answer
	Option: C Explanation : In demultiplexer, inputs is inserted serially and then it gives multiple outputs which are in parallel form. .

22: An OR gate can be imagined as

A.	Switches connected in series
B.	Switches connected in parallel
C.	MOS transistors connected in series
D.	None of these
	Answer
	Option: B Explanation : .

23: Which combination of gates does not allow the implementation of an arbitrary boolean function?

A.	OR gates and AND gates only
B.	OR gates and exclusive OR gate only
C.	OR gates and NOT gates only
D.	NAND gates only
	Answer
	Option: A Explanation : .

24:

How many full adders are required to construct an m-bit parallel adder ?

A.	m/2
B.	m-1
C.	m
D.	m+1
	Answer
	Option: B Explanation : We need an adder for every bit. So we should need m full adders. A full adder adds a carry bit to two inputs and produces an output and a carry. But the most significant bits can use a half adder, which differs from the full adder as in that it has no carry input, so we need m-1 full adders in m bit parllel adder. .

25: Parallel adders are

A.	combinational logic circuits
B.	sequential logic circuits
C.	both (a) and (b)
D.	None of these
	Answer
	Option: A Explanation :.

26:

The digital multiplexer is basically a combination logic circuit to perform the operation

A.	AND-AND
B.	OR-OR
C.	AND-OR
D.	OR-AND
	Answer
	Option: C Explanation : The equation for digital multiplexer includes AND and OR operations . For example AB+CD. So here firstly we have to solve AND operation then OR operation. Option is 'C'. .

27: The output of NOR gate is

A.	High if all of its inputs are high
B.	Low if all of its inputs are low
C.	High if all of its inputs are low
D.	High if only of its inputs is low
	Answer
	Option: C Explanation : .

28: How many lines the truth table for a four-input NOR gate would contain to cover all possible input combinations ?

A.	4
B.	8
C.	12
D.	16
	Answer
	Option: D Explanation : .

29:

A toggle operation cannot be performed using a single

A.	NOR gate
B.	AND gate
C.	NAND gate
D.	XOR gate
	Answer
	Option: B Explanation : For XOR gate complements the sinlge input eg if input 1 is given then you get 1 in output and vice versa This is called toggling. Nand and NOR are universal gates and can be used to design XOR gate so they can also perform toggle operation. Therefore correct answer is AND gate. .

30: Which table shows the electrical state of a digital circuit's output for every possible combination of electrical states in the inputs ?

A.	Function table
B.	Truth table
C.	Routing table
D.	ASCII table
	Answer
	Option: A Explanation : .

31:

What is the minimum number of 2 input NAND gates required to implement the function
F = (x'+y') (z+w)

A.	6
B.	5
C.	4
D.	3
	Answer
	Option: C Explanation : .

32: How many truth tables can be made from one function table ?

A.	One
B.	Two
C.	Three
D.	Any numbers
	Answer
	Option: B Explanation : .

33: A comparison between serial and parallel adder reveals that serial order

A.	is slower
B.	is faster
C.	operates at the same speed as parallel adder
D.	is more complicated
	Answer
	Option: A Explanation : .

34: What is the largest number of data inputs which a data selector with two control inputs can have ?

A.	2
B.	4
C.	8
D.	16
	Answer
	Option: B Explanation : .

35: If a logic gates has four inputs, then total number of possible input combinations is

A.	4
B.	8
C.	16
D.	32
	Answer
	Option: C Explanation : .

36: A combinational circuit is one in which the output depends on the

A.	input combination at the time
B.	input combination and the previous output
C.	input combination at that time and the previous input combination
D.	present output and the previous output
	Answer
	Option: A Explanation : .

37: The function of a multiplexer is

A.	to decode information
B.	to select 1 out of N input data sources and to transmit it to single channel
C.	to transit data on N lines
D.	to perform serial to parallel conversion
	Answer
	Option: B Explanation : .

38:

A combinational logic circuit which generates a particular binary word or number is

A.	Decoder
B.	Multiplexer
C.	Encoder
D.	Demultiplexer
	Answer
	Option: A Explanation : .

39: Which of the following circuit can be used as parallel to serial converter ?

A.	Multiplexer
B.	Demultiplexer
C.	Decoder
D.	Digital counter
	Answer
	Option: A Explanation : .

40:

In which of the following adder circuits, the carry look ripple delay is eliminated ?

A.	Half adder
B.	Full adder
C.	Parallel adder
D.	Carry-look-ahead adder
	Answer
	Option: D Explanation : .

41: Adders

A.	adds 2 bits
B.	is called so because a full adder involves two half-adders
C.	needs two input and generates two output
D.	All of these
	Answer
	Option: D Explanation : .

42: The inverter OR-gate and AND gate are called deeision-making elements because they can recognize some input while disregarding others. A gate recognize a word when its output is

A.	words,high
B.	bytes,low
C.	bytes,high
D.	character,low
	Answer
	Option: A Explanation : .

43: Which one of the following set of gates are best suited for 'parity' checking and 'parity' generation.

A.	AND, OR, NOT gates
B.	EX-NOR or EX-OR gates
C.	NAND gates
D.	NOR gates
	Answer
	Option: B Explanation : .

44: An AND circuit

A.	is a memory circuit
B.	gives an output when all input signals are present simultaneously
C.	is a -ve OR gate
D.	is a linear circuit
	Answer

45: Which of the following adders can add three or more numbers at a time ?

A.	Parallel adder
B.	Carry-look-ahead adder
C.	Carry-save-adder
D.	Full adder
	Answer
	Option: C Explanation : .

46:

Which one of the following logic expression is incorrect?

A.	1 ⊕ 0 = 1
B.	1 ⊕ 1 ⊕ 0 = 1
C.	1 ⊕ 1 ⊕ 1 = 1
D.	1 ⊕ 1 = 0
	Answer
	Option: B Explanation : .

47:

The circuit shown in the figure is equivalent to?

A.
B.
C.
D.
	Answer
	Option: B Explanation : .

48:

The black box in the following figure consists of a minimum complexity circuit that uses only AND,OR and NOT gates. The function f (x,y,z) = 1 whenever x , y are different and 0 otherwise. In addition the 3 inputs x,y,z are never all the same value. Which of the following equation lead to the correct design for the minimum complexity circuit?

A.	x'y + xy'
B.	x + y'z
C.	x'y'z' + xy'z
D.	xy + y'z + z'
	Answer
	Option: A Explanation : .

49:

If A ⊕ B = C, then

A.	A ⊕ C = B
B.	B ⊕ C = A
C.	A ⊕ B ⊕ C = 0
D.	Both (a) & (b)
	Answer
	Option: D Explanation : Mathematically, XOR is both associative and commutative ie. If C = A XOR B then B = C XOR A or B = A XOR C and and A = B XOR C A = C XOR B .

50:

To make the following circuit a tautology ? marked box should be

A.	OR gate
B.	AND gate
C.	NAND gate
D.	EX-OR GATE
	Answer
	Option: C Explanation : The output f = (x+x')+(y+y'). Starting derivation using 'f'. -->(x+x')+(y+y') -->(x+y)+(x'+y') -->(Already a known Input)+(x'+y') So, the unknown input is (x'+y'). This can be made by :- x and y fed into a NOT gate and then AND gate to become (x'+y'). So the answer is NAND gate. .

51:

For the circuit shown for AB = 00, AB = 01, C, S values respectively are

A.	0 , 0 and 0, 1
B.	0, 0 and 1, 0
C.	0, 1 and 0, 0
D.	1, 0 and 0, 0
	Answer

52:

What logic gate is represented by the circuit shown below?

A.	NAND
B.	NOR
C.	AND
D.	EQUIVALENCE
	Answer

53:

The circuit shown below is the

A.	Full adder
B.	Full subtractor
C.	Parity checker
D.	None of these
	Answer

54:

In the following gate network which gate is redundant

A.	Gate no. 1
B.	Gate no. 2
C.	Gate no. 3
D.	Gate no. 4
	Answer

55:

The combinational circuit given below is implemented with two NAND gates. To which of the following individual gates is its equivalent?

A.	NOT
B.	OR
C.	AND
D.	XOR
	Answer

56:

What logic function is performed by the circuit shown below?

A.	Ring counter
B.	Ripple counter
C.	Full adder
D.	Half adder
	Answer
	Option: D Explanation : Here total 7 NAND gates are present and in half adder one AND and one EX-OR gate are required. In turn one EX-OR gate can be built by 5 NAND where as one AND gate can be built by 2 NAND gates so this is diagram of half adder. So the answer is (D). .

57:

What is the Boolean expression for the following circuit?

A.	F(A, B) = ( A + B' )' . ( B + A' )'
B.	F( A, B ) = 1 ( Tautology )
C.	F( A, B ) = ⊕ ( inconsistency)
D.	F ( A, B ) = A ⊕ B ( A exclusive OR'ed with B)
	Answer
	Option: A Explanation : Ans is A as input to 1st OR gate is A, and B' so output of 1st OR gate is (A+B') In the same way output for 2nd OR gate is (A'+B) So Final output will be (A+B')'. (A'+B)' .

58:

In the circuit shown below, which logic function does this circuit generate?

A.	AND
B.	NOR
C.	NAND
D.	OR
	Answer
	Option: D Explanation : .

59:

Output of the following circuit is

A.	0
B.	1
C.	x
D.	x'
	Answer
	Option: A Explanation : Truth Table for XOR .

60:

A small dot or circle printed on top of an IC indicates

A.	V_cc
B.	G_nd
C.	Pin 14
D.	Pin 1
	Answer
	Option: D Explanation : .

61:

The number of two input multiplexers required to construct a 210 input multiplexer is,

A.	31
B.	10
C.	127
D.	1023
	Answer
	Option: D Explanation : .

62:

The full adder adds the Kth bits of two numbers to the

A.	difference of the previous bits
B.	sum of all previous bits
C.	carry from ( K - 1 )^TH bit
D.	sum of previous bit
	Answer
	Option: C Explanation : .

63:

In the following question, match each of the items A, B and C on the left with an approximation item on the right

A. Shift register can be used 1. for code conversion

B. A multiplexer can be used 2. to generate memory slipto select

C. A decoder can be used 3. for parallel to serial conversion

4. as many to one switch

5. for analog to digital conversion

A.	A B C 1 2 3
B.	A B C 3 4 1
C.	A B C 5 4 2
D.	A B C 1 3 5
	Answer
	Option: B Explanation : .

64:

A full-adder is a logic circuit which can add two single order bits plus a carry in from a previous adder. Its incomplete truth table is given in the table below. The missing entry in the outputs for SUM and CARRY out are

Input				Outputs
A	A	B	Cin	Sum	Carry_OUT
0	0	0	0	0	0
0	0	0	1	1	0
0	0	1	0	1	0
0	0	1	1	0	1
1	1	0	0	1	0
1	1	0	1	0	1
1	1	1	0	0	1
1	1	1	1	?	?

A.	0 0
B.	0 1
C.	1 0
D.	1 1
	Answer
	Option: D Explanation : .

65:

Extremely low power dissipation and low cost per gate can be achieved in:

A.	MOS ICs
B.	C MOS ICs
C.	TTL ICs
D.	ECL ICs
	Answer
	Option: B Explanation : .

66:

An example of a universal building block is:

A.	EX-OR gate
B.	AND gate
C.	OR gate
D.	NOR gate
	Answer
	Option: D Explanation : .

67:

The dual ofthe switching function x + yz is:

A.	x+yz
B.	x̄ + ȳz̄
C.	x(y+z)
D.	x̄(ȳ + z̄)
	Answer
	Option: C Explanation : .

68:

The characteristic equation of D flip-flop is:

A.	Q = 1
B.	Q = 0
C.	Q = D̄
D.	Q= D
	Answer
	Option: D Explanation : .

69:

If four 4 input multiplexers drive a 4 input multiplexer, we get a:

A.	16 input MUX
B.	8 input MUX
C.	4 input MUX
D.	2 input MUX
	Answer
	Option: A Explanation : .

Allan.J.Wilson

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Sunday, 22 November 2020

Digital Logic Circuits MCQs

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