1:
In which of the
following gates, the output is 1, if and only if at least one input is 1?
|
NOR |
|
|
AND |
|
|
OR |
|
|
NAND |
|
|
|
|
|
|
Option: C Explanation : In OR gate we need atleast one
bit to be equal to 1 to generate the output as 1 because OR means any
of the condition out of two is equal to 1 which means if atleast
one input is 1 then it shows output as 1 . Number of 1's in input may be more
than one but the output will always be 1 in OR gate. So the answer is 'C'. . |
2: The time
required for a gate or inverter to change its state is called
|
Rise
time |
|
|
Decay
time |
|
|
Propagation
time |
|
|
Charging
time |
|
|
|
|
|
|
Option: C Explanation : . |
3: The time
required for a pulse to change from 10 to 90 percent of its maximum value is
called
|
Rise
time |
|
|
Decay
time |
|
|
Propagation
time |
|
|
Operating
speed |
|
|
|
|
|
|
Option: A Explanation : . |
4: The
maximum frequency at which digital data can be applied to gate is caled
|
Operating
speed |
|
|
Propagation
speed |
|
|
Binary
level transaction period |
|
|
Charging
time |
|
|
|
|
|
|
Option: A Explanation : . |
5:
What is the minimum
number of two-input NAND gates used to perform the function of two input OR
gate ?
|
one |
|
|
two |
|
|
three |
|
|
four |
|
|
|
|
|
|
Option: C Explanation : Y=A+B. This is the equation of OR gate. We require 3 NAND gates to
create OR gate. We can also write After 1st NAND operation So we need 3 NAND gates. |
6: Odd parity
of word can beconveniently tested by
|
OR gate |
|
|
AND
gate |
|
|
NOR
gate |
|
|
XOR
gate |
|
|
|
|
|
|
Option: D Explanation : . |
7:
Identify the logic
function performed by the circuit shown in the given figure
|
Exclusive OR |
|
|
Exclusive NOR |
|
|
NAND |
|
|
NOR |
|
|
|
|
|
|
Option: B Explanation : . |
8: Which one
of the following will give the sum of full adders as output ?
|
Three
point majority circuit |
|
|
Three
bit parity checker |
|
|
Three
bit comparator |
|
|
Three
bit counter |
|
|
|
|
|
|
Option: D Explanation : . |
9:
The number of full
and half-adders required to add 16-bit numbers is
|
8 half-adders, 8 full-adders |
|
|
1 half-adder, 15 full-adders |
|
|
16 half-adders, 0 full-adders |
|
|
4 half-adders, 12 full-adders |
|
|
|
|
|
|
Option: B Explanation : The one half-adder can add the least significant bit of the two
numbers. Full adders are required to add the remaining 15 bits as they all
involve adding carries. . |
10: The time
required for a pulse to decrease from 90 to 10 per cent of its maximum value is
called
|
Rise
time |
|
|
Decay
time |
|
|
Binary
level transition period |
|
|
Propagation
delay |
|
|
|
|
|
|
Option: B Explanation : . |
11: Which of
the following gates would output 1 when one input is 1 and other input is 0 ?
|
OR gate |
|
|
AND
gate |
|
|
NAND
gate |
|
|
both
(a) and (c) |
|
|
|
|
|
|
Option: D Explanation : . |
12: Which of
the following statements is wrong ?
|
Propagation
delay is the time required for a gate to change its state |
|
|
Noise
immunity is the amount of noise which can be applied to the input of a gate
without causing the gate to change state |
|
|
Fan-in
of a gate is always equal to fan-out of the same gate |
|
|
Operating
speed is the maximum frequency at which digital data can be applied to a gate |
|
|
|
|
|
|
Option: C Explanation : . |
13:
Which of the following
expressions is not equivalent to X ' ?
|
X NAND X |
|
|
X NOR X |
|
|
X NAND 1 |
|
|
X NOR 1 |
|
|
|
|
|
|
Option: D Explanation : Answer is C as In Option (d) . |
14: Which of
the following gates are added to the inputs of the OR gate to convert it to the
NAND gate ?
|
NOT |
|
|
AND |
|
|
OR |
|
|
XOR |
|
|
|
|
|
|
Option: A Explanation : . |
15: The
EXCLUSIVE NOR gate is equivalent to which gate followed by an inverter ?
|
OR |
|
|
AND |
|
|
NAND |
|
|
XOR |
|
|
|
|
|
|
Option: D Explanation : . |
16:
A one-to-four line demultiplexer is to be implemented using a memory.
How many bits must each word have ?
|
1 bit |
|
|
2 bits |
|
|
4 bits |
|
|
8 bits |
|
|
|
|
|
|
Option: A Explanation : 2 select line A and B will work as address lines, so we have 4
addresses (or words) Each word will have 4 bits so memory required is 4 x 4 = 16 bits . |
17: What logic function is produced by adding an inverter to the
output of an AND gate ?
|
NAND |
|
|
NOR |
|
|
XOR |
|
|
OR |
|
|
|
|
|
|
Option: A Explanation : . |
18: Which of the following gates is known as coincidence detector
?
|
AND
gate |
|
|
OR gate |
|
|
NOT
gate |
|
|
NAND
gate |
|
|
|
|
|
|
Option: A Explanation : . |
19: Which table shows the logical state of a digital circuit
output for every possible combination of logical states in the inputs ?
|
Function
table |
|
|
Truth
table |
|
|
Routing
table |
|
|
ASCII
table |
|
|
|
|
|
|
Option: B Explanation : . |
20:
A positive AND gate is also a negative
|
NAND gate |
|
|
NOR gate |
|
|
AND gate |
|
|
OR gate |
|
|
|
|
|
|
Option: D Explanation : Truth Table For AND 0
0 => 0 0
1 => 0 1
0 => 0 1
1 => 1 Now
invert all values (as if you place inverters on the two inputs and the one
output): 1
1 => 1 1
0 => 1 0
1 => 1 0
0 => 0 . |
21:
A demultiplexer is
used to
|
Route the data from single
input to one of many outputs |
|
|
Perform serial to parallel
conversion |
|
|
Both (a) & (b) |
|
|
Select data from several inputs
and route it to single output |
|
|
|
|
|
|
Option: C Explanation : In demultiplexer, inputs is inserted serially and then it gives
multiple outputs which are in parallel form. . |
22: An OR
gate can be imagined as
|
Switches
connected in series |
|
|
Switches
connected in parallel |
|
|
MOS
transistors connected in series |
|
|
None of
these |
|
|
|
|
|
|
Option: B Explanation : . |
23: Which
combination of gates does not allow the implementation of an arbitrary boolean
function?
|
OR
gates and AND gates only |
|
|
OR
gates and exclusive OR gate only |
|
|
OR
gates and NOT gates only |
|
|
NAND
gates only |
|
|
|
|
|
|
Option: A Explanation : . |
24:
How many full adders
are required to construct an m-bit parallel adder ?
|
m/2 |
|
|
m-1 |
|
|
m |
|
|
m+1 |
|
|
|
|
|
|
Option: B Explanation : We need an adder for every bit. So we should need m full adders.
A full adder adds a carry bit to two inputs and produces an output and a
carry. . |
25: Parallel
adders are
|
combinational
logic circuits |
|
|
sequential
logic circuits |
|
|
both
(a) and (b) |
|
|
None of
these |
|
|
|
|
|
|
Option: A Explanation :. |
26:
The digital
multiplexer is basically a combination logic circuit to perform the operation
|
AND-AND |
|
|
OR-OR |
|
|
AND-OR |
|
|
OR-AND |
|
|
|
|
|
|
Option: C Explanation : The equation for digital multiplexer includes AND and OR operations .
For example AB+CD. So here firstly we have to solve AND operation then OR
operation. Option is 'C'. . |
27: The
output of NOR gate is
|
High if
all of its inputs are high |
|
|
Low if
all of its inputs are low |
|
|
High if
all of its inputs are low |
|
|
High if
only of its inputs is low |
|
|
|
|
|
|
Option: C Explanation : . |
28: How many
lines the truth table for a four-input NOR gate would contain to cover all
possible input combinations ?
|
4 |
|
|
8 |
|
|
12 |
|
|
16 |
|
|
|
|
|
|
Option: D Explanation : . |
29:
A toggle operation
cannot be performed using a single
|
NOR gate |
|
|
AND gate |
|
|
NAND gate |
|
|
XOR gate |
|
|
|
|
|
|
Option: B Explanation : For XOR gate complements the sinlge input eg if input 1 is
given then you get 1 in output and vice versa This is called toggling. Nand and NOR are universal gates and can be used to design XOR
gate so they can also perform toggle operation. Therefore correct answer is AND gate. . |
30: Which
table shows the electrical state of a digital circuit's output for every
possible combination of electrical states in the inputs ?
|
Function
table |
|
|
Truth
table |
|
|
Routing
table |
|
|
ASCII
table |
|
|
|
|
|
|
Option: A Explanation : . |
31:
What is the minimum
number of 2 input NAND gates required to implement the function
F = (x'+y') (z+w)
|
6 |
|
|
5 |
|
|
4 |
|
|
3 |
|
|
|
|
|
|
Option: C Explanation : . |
32: How many
truth tables can be made from one function table ?
|
One |
|
|
Two |
|
|
Three |
|
|
Any
numbers |
|
|
|
|
|
|
Option: B Explanation : . |
33: A
comparison between serial and parallel adder reveals that serial order
|
is
slower |
|
|
is
faster |
|
|
operates
at the same speed as parallel adder |
|
|
is more
complicated |
|
|
|
|
|
|
Option: A Explanation : . |
34: What is
the largest number of data inputs which a data selector with two control inputs
can have ?
|
2 |
|
|
4 |
|
|
8 |
|
|
16 |
|
|
|
|
|
|
Option: B Explanation : . |
35: If a
logic gates has four inputs, then total number of possible input combinations
is
|
4 |
|
|
8 |
|
|
16 |
|
|
32 |
|
|
|
|
|
|
Option: C Explanation : . |
36: A
combinational circuit is one in which the output depends on the
|
input
combination at the time |
|
|
input
combination and the previous output |
|
|
input
combination at that time and the previous input combination |
|
|
present
output and the previous output |
|
|
|
|
|
|
Option: A Explanation : . |
37: The
function of a multiplexer is
|
to
decode information |
|
|
to
select 1 out of N input data sources and to transmit it to single channel |
|
|
to
transit data on N lines |
|
|
to
perform serial to parallel conversion |
|
|
|
|
|
|
Option: B Explanation : . |
38:
A combinational
logic circuit which generates a particular binary word or number is
|
Decoder |
|
|
Multiplexer |
|
|
Encoder |
|
|
Demultiplexer |
|
|
|
|
|
|
Option: A Explanation : . |
39: Which of
the following circuit can be used as parallel to serial converter ?
|
Multiplexer |
|
|
Demultiplexer |
|
|
Decoder |
|
|
Digital
counter |
|
|
|
|
|
|
Option: A Explanation : . |
40:
In which of the
following adder circuits, the carry look ripple delay is eliminated ?
|
Half adder |
|
|
Full adder |
|
|
Parallel adder |
|
|
Carry-look-ahead adder |
|
|
|
|
|
|
Option: D Explanation : . |
41: Adders
|
adds 2
bits |
|
|
is
called so because a full adder involves two half-adders |
|
|
needs
two input and generates two output |
|
|
All of
these |
|
|
|
|
|
|
Option: D Explanation : . |
42: The
inverter OR-gate and AND gate are called deeision-making elements because they
can recognize some input while disregarding others. A gate recognize a word
when its output is
|
words,high |
|
|
bytes,low |
|
|
bytes,high |
|
|
character,low |
|
|
|
|
|
|
Option: A Explanation : . |
43: Which one
of the following set of gates are best suited for 'parity' checking and
'parity' generation.
|
AND,
OR, NOT gates |
|
|
EX-NOR
or EX-OR gates |
|
|
NAND
gates |
|
|
NOR
gates |
|
|
|
|
|
|
Option: B Explanation : . |
44: An AND
circuit
|
is a
memory circuit |
|
|
gives
an output when all input signals are present simultaneously |
|
|
is a
-ve OR gate |
|
|
is a
linear circuit |
|
|
|
|
|
|
45: Which of
the following adders can add three or more numbers at a time ?
|
Parallel
adder |
|
|
Carry-look-ahead
adder |
|
|
Carry-save-adder |
|
|
Full
adder |
|
|
|
|
|
|
Option: C Explanation : . |
46:
Which one of
the following logic expression is incorrect?
|
1 ⊕ 0
= 1 |
|
|
1 ⊕ 1
⊕ 0 = 1 |
|
|
1 ⊕ 1 ⊕ 1
= 1 |
|
|
1 ⊕ 1
= 0 |
|
|
|
|
|
|
Option: B Explanation : . |
47:
The circuit
shown in the figure is equivalent to?
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Option: B Explanation : . |
48:
The black box in
the following figure consists of a minimum complexity circuit that uses only
AND,OR and NOT gates. The function f (x,y,z) = 1 whenever x , y are different
and 0 otherwise. In addition the 3 inputs x,y,z are never all the same value.
Which of the following equation lead to the correct design for the minimum
complexity circuit?
|
x'y + xy' |
|
|
x + y'z |
|
|
x'y'z' + xy'z |
|
|
xy + y'z + z' |
|
|
|
|
|
|
Option: A Explanation : . |
49:
If A ⊕ B = C, then
|
A ⊕ C = B |
|
|
B ⊕ C = A |
|
|
A ⊕
B ⊕ C = 0 |
|
|
Both (a) & (b) |
|
|
|
|
|
|
Option: D Explanation : Mathematically, XOR is both
associative and commutative ie. If C = A XOR B then B = C XOR A or B = A
XOR C and and A = B XOR C A = C XOR B . |
50:
To make the
following circuit a tautology ? marked box should be
|
OR gate |
|
|
AND gate |
|
|
NAND gate |
|
|
EX-OR GATE |
|
|
|
|
|
|
Option: C Explanation : The output f = (x+x')+(y+y'). Starting derivation using 'f'. -->(x+x')+(y+y') -->(x+y)+(x'+y') -->(Already a known Input)+(x'+y') So, the unknown input is (x'+y'). This can be made by :- x and y fed into a NOT gate and then AND gate to become (x'+y'). So the answer is NAND gate. . |
51:
For the
circuit shown for AB = 00, AB = 01, C, S values respectively are
|
0 , 0 and 0, 1 |
|
|
0, 0 and 1, 0 |
|
|
0, 1 and 0, 0 |
|
|
1, 0 and 0, 0 |
|
|
|
|
|
|
52:
What logic gate
is represented by the circuit shown below?
|
NAND |
|
|
NOR |
|
|
AND |
|
|
EQUIVALENCE |
|
|
|
|
|
|
53:
The circuit shown
below is the
|
Full adder |
|
|
Full subtractor |
|
|
Parity checker |
|
|
None of these |
|
|
|
|
|
|
54:
In the
following gate network which gate is redundant
|
Gate no. 1 |
|
|
Gate no. 2 |
|
|
Gate no. 3 |
|
|
Gate no. 4 |
|
|
|
|
|
|
55:
The combinational
circuit given below is implemented with two NAND gates. To which of the
following individual gates is its equivalent?
|
NOT |
|
|
OR |
|
|
AND |
|
|
XOR |
|
|
|
56:
What logic
function is performed by the circuit shown below?
|
Ring counter |
|
|
Ripple counter |
|
|
Full adder |
|
|
Half adder |
|
|
|
|
|
|
Option: D Explanation : Here total 7 NAND gates are present and in half adder one AND
and one EX-OR gate are required. . |
57:
What is the Boolean
expression for the following circuit?
|
F(A, B) = ( A + B' )' . ( B +
A' )' |
|
|
F( A, B ) = 1 ( Tautology ) |
|
|
F( A, B ) = ⊕ (
inconsistency) |
|
|
F ( A, B ) = A ⊕
B ( A exclusive OR'ed with B) |
|
|
|
|
|
|
Option: A Explanation : Ans is A as input to 1st OR gate is A, and B'
so output of 1st OR gate is (A+B') In the same way output for
2nd OR gate is (A'+B) So Final output will be (A+B')'. (A'+B)' . |
58:
In the
circuit shown below, which logic function does this circuit generate?
|
AND |
|
|
NOR |
|
|
NAND |
|
|
OR |
|
|
|
|
|
|
Option: D Explanation : . |
59:
Output of the
following circuit is
|
0 |
|
|
1 |
|
|
x |
|
|
x' |
|
|
|
|
|
|
Option: A Explanation : Truth Table for XOR
. |
60:
A small dot or
circle printed on top of an IC indicates
|
Vcc |
|
|
Gnd |
|
|
Pin 14 |
|
|
Pin 1 |
|
|
|
|
|
|
Option: D Explanation : . |
61:
The number of
two input multiplexers required to construct a 210 input multiplexer is,
|
31 |
|
|
10 |
|
|
127 |
|
|
1023 |
|
|
|
|
|
|
Option: D Explanation : . |
62:
The full
adder adds the Kth bits of two numbers to the
|
difference of the previous bits |
|
|
sum of all previous bits |
|
|
carry from ( K - 1 )TH bit |
|
|
sum of previous bit |
|
|
|
|
|
|
Option: C Explanation : . |
63:
In the
following question, match each of the items A, B and C on the left with an
approximation item on the right
A. Shift register
can be used 1. for
code conversion
B. A
multiplexer can be used 2. to
generate memory slipto select
C. A decoder can be
used 3. for
parallel to serial conversion
4. as many
to one switch
5. for
analog to digital conversion
|
A B C 1 2 3 |
|
|
A B C 3 4 1 |
|
|
A B C 5 4 2 |
|
|
A B C 1 3 5 |
|
|
|
|
|
|
Option: B Explanation : . |
64:
A full-adder
is a logic circuit which can add two single order bits plus a carry in from a
previous adder. Its incomplete truth table is given in the table below. The
missing entry in the outputs for SUM and CARRY out are
|
Input |
Outputs |
||||
|
A |
A |
B |
Cin |
Sum |
CarryOUT |
|
0 |
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
0 |
1 |
1 |
0 |
|
0 |
0 |
1 |
0 |
1 |
0 |
|
0 |
0 |
1 |
1 |
0 |
1 |
|
1 |
1 |
0 |
0 |
1 |
0 |
|
1 |
1 |
0 |
1 |
0 |
1 |
|
1 |
1 |
1 |
0 |
0 |
1 |
|
1 |
1 |
1 |
1 |
? |
? |
|
0 0 |
|
|
0 1 |
|
|
1 0 |
|
|
1 1 |
|
|
|
|
|
|
Option: D Explanation : . |
65:
Extremely low power
dissipation and low cost per gate can be achieved in:
|
MOS ICs |
|
|
C MOS ICs |
|
|
TTL ICs |
|
|
ECL ICs |
|
|
|
|
|
|
Option: B Explanation : . |
66:
An example of a
universal building block is:
|
EX-OR gate |
|
|
AND gate |
|
|
OR gate |
|
|
NOR gate |
|
|
|
|
|
|
Option: D Explanation : . |
67:
The dual ofthe
switching function x + yz is:
|
x+yz |
|
|
x̄ + ȳz̄ |
|
|
x(y+z) |
|
|
x̄(ȳ + z̄) |
|
|
|
|
|
|
Option: C Explanation : . |
68:
The characteristic
equation of D flip-flop is:
|
Q = 1 |
|
|
Q = 0 |
|
|
Q = D̄ |
|
|
Q= D |
|
|
|
|
|
|
Option: D Explanation : . |
69:
If four 4 input
multiplexers drive a 4 input multiplexer, we get a:
|
16 input MUX |
|
|
8 input MUX |
|
|
4 input MUX |
|
|
2 input MUX |
|
|
|
|
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Option: A Explanation : . |
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